A Method to Implement Layout Versus Schematic Check in Integrated Circuits Design Programs

In this paper, a new method to implement the LVS check in different IC design software, without using specialized LVS software, is presented. The main advantage of the proposed method consists in the fact that all types of checkings (DRC and LVS) can be easily performed, without using specialized parameters extraction software, which is very expensive and difficult to implement. The method principle is based on the ability of certain IC design software (like L-Edit) to display in layout design the electric connections between basic cells (even at a transistor’s level) and also to permanently monitoring the routed wires and also of those remained to be routed. In order to export the electrical scheme (designed with specialized software, as OrCAD or SPICE) in layout, there have to be passed few well defined stages, which will be presented in detail in the paper. After a successful trespassing of those stages, all cells of the electric scheme will be imported in layout design and the electric connections between them will be also displayed. Connectivity is displayed as a network of routing guides for the pin-to-pin connections. Throughout the layout design process, the connectivity display is interactively updated as objects are moved and new wire is added. In this way, the LVS is checked in real time, when assisted manual routing is performed. Finally, all layout design stages are illustrated, using as example a circuit implemented into 0.8 μm BiCMOS technology.